Stacked die package

ABSTRACT

The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.

RELATED APPLICATION

The present application is a continuation of U.S. patent applicationSer. No. 13/231,953, filed on Sep. 13, 2011, entitled “STACKED DIEPACKAGE”, which is a Divisional of U.S. application Ser. No. 11/852,904,filed on Sep. 10, 2007, entitled “STACKED DIE PACKAGE”, now issued U.S.Pat. No. 8,044,497, issued on Oct. 25, 2011.

BACKGROUND

As performance increases and electronic device sizes decrease, problemsrelating to the connections between multiple die structures and betweendie structures and other elements have developed. For example, suchproblems may relate to the undesirably long path that metal tracestravel to reach active regions on a die, due to the system architecture.Problems may also relate to the lower die in a stacked die structurecarrying the entire power source for the upper die(s), which can createundesirable thermal stresses. Conventional stacked die structures mayalso have problems relating to the height of the assembly, with theinterconnection between the stacked die structures being undesirablylarge.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are described by way of example, with reference to theaccompanying drawings, which are not drawn to scale, wherein:

FIG. 1 illustrates an electronic assembly including first and second diestructures stacked backside surface to backside surface, in accordancewith certain embodiments;

FIG. 2 illustrates a detailed view of region A of FIG. 1, in accordancewith certain embodiments;

FIG. 3 illustrates a flow chart of operations for forming an electronicassembly including first and second die structures stacked backsidesurface to backside surface, in accordance with certain embodiments;

FIG. 4 illustrates a die structure in accordance with certainembodiments;

FIGS. 5(A)-5(J) illustrate processing operations for forming a diestructure including metallization layers on a backside surface thereof,in accordance with certain embodiments;

FIG. 6 illustrates an assembly including first and second die structuresstacked backside surface to backside surface on a substrate, in whichthe second die structure is wire bonded to the substrate, in accordancewith certain embodiments;

FIG. 7 illustrates an assembly including first, second, and thirdstructures, in which two of the structures are stacked backside surfaceto backside surface on a substrate, in accordance with certainembodiments;

FIG. 8 is an electronic system arrangement in which certain embodimentsmay find application.

DETAILED DESCRIPTION

Certain embodiments relate to electronic device assemblies and methodsfor their manufacture. Embodiments may include the use of first andsecond die structures stacked with the backside metallization surface ofthe second die structure positioned on the backside metallizationsurface of the first die structure.

FIG. 1 illustrates an embodiment including an electronic assembly 10including a first semiconductor die structure 20 and a secondsemiconductor die structure 30 positioned thereon. The die structures20, 30 may be formed to include similar electronic devices formedtherein or may be formed to include different electronic devices. Thedie structures 20, 30 each include a front side active region 28, 38 anda backside metallization region including backside metal regions 24, 34and backside dielectric regions 26, 36. The front side active region mayinclude devices such as transistors and the like formed in and on thesemiconductor die, as well as metal and dielectric layers formedthereon. The die structures also each include a plurality of vias 22, 32that electrically couple the front side active regions 28, 38 to thebackside metal regions 24, 34. The vias 22, 32 include an electricallyconductive material such as a metal, that either partially or completelyfills the vias 22, 32 and acts to transmit electrical signalstherethrough. Examples of via fill materials include, but are notlimited to, metals such as aluminum, copper, silver, gold, andcombinations thereof.

As illustrated in FIG. 1, the die structures 20, 30 are positioned sothat the backside metallization regions of each are facing each other.The outermost surface of the backside metallization regions of the diestructures 20, 30 include metal regions 24, 34 and dielectric regions26, 36. The surfaces may be coupled to each other using a suitablemethod. In certain embodiments, a surface activated bonding (SAB)technique is used. In typical SAB techniques, two solid surfaces arecleaned atomically using ions such as Argon ions, or using a fast atombeam, in an ultra high vacuum (UHV) chamber at room temperature. Whenthe surfaces are brought into close contact with each other, an adhesiondevelops between the atoms of the cleaned surfaces. In otherembodiments, other types of electrical interconnection techniques may beused to couple the backside of a first die structure to the backside ofa second die structure, including, for example, solder bump bonding.

The stacked die structures 20, 30 may be positioned on a substrate 40,and coupled to the substrate 40 using any suitable technique, forexample, using solder bump connections 42. The substrate 40 may beformed from materials including, but not limited to, polymer and ceramicmaterials. A suitable underfill material 44 may be positioned around andbetween the die structure 20 and the substrate 40. In the embodimentillustrated in FIGS. 1-2, the underfill material 44 may flow a distanceup at least some of the side surfaces of the die structure 20. Anexample of a suitable underfill material 44 is a polymer epoxy. Theunderfill material 44 may be dispensed using a suitable methodincluding, but not limited to, capillary dispense, lamination, spindispense, and jet dispense. A molding compound 46, for example, apolymer, may be formed to cover exposed portions of the substrate 40 andthe stacked die structures 20, 30. The assembly 10 may be coupled toanother structure, such as a board, using any suitable technique, forexample, using solder bump connections 48.

FIG. 2 illustrates a blown-up view of region A of FIG. 1. The activeregions 28, 38 of the die structures 20, 30 may include a plurality oflayers, including one or more layers 25, 35 that include electronicdevices such as transistors and the like, as well as a plurality oflayers including metal regions 23, 33 and dielectric regions 21, 31.Within a single layer, the dielectric regions 21, 31 may be positionedbetween metal regions 23, 33. The metal regions 23, 33 and thedielectric regions 21, 31 may be formed using any suitable CMOSprocessing methods. The term metal as used herein includes pure metalsand alloys. The term dielectric as used herein includes materials formedfrom electrically insulating materials including, but not limited to,oxides and polymers.

The active region 28 of the die structure 20 (the lower die structure inFIGS. 1-2) is coupled to the substrate 40 through the solder bump bonds42. The active region 38 of the die structure 30 (the upper diestructure in FIGS. 1-2) may be electrically coupled to other devices(not shown in FIGS. 1-2), for example, a third semiconductor diestructure. Such a device may be electrically coupled to the diestructure 30 using any suitable technique, for example, a solder bumpconnection technique or a surface activated bonding technique.Alternatively, the active region 38 of the die structure 30 may beelectrically coupled to the substrate 40 using, for example, wire bonds.

FIG. 3 illustrates a flow chart of operations for forming a stacked dieassembly in accordance with certain embodiments. Box 80 is thinning asilicon semiconductor wafer from the backside, which may be done afterformation of an active region and plurality of vias. Box 82 is formingthe backside metallization, which may include forming both metal anddielectric layers. An example of process operations for forming abackside metallization region is described below, in connection withFIGS. 4 and 5(A)-5(J). Box 84 is attaching a bottom die to a packagesubstrate. This may be carried out using any suitable technique, forexample, bump bonding. Box 86 is providing an underfill material that ispositioned between the bottom die and the package substrate. Box 88 isattaching a top die to the bottom die with a back side metallizationsurface of the first die facing a backside metallization surface of thesecond die. The attachment may be carried out using a suitable surfaceactive bonding (SAB) technique. Box 90 is providing a package moldingmaterial such as a polymer, that covers the bottom and top diestructures and the package substrate. The order of at least some of theoperations specified in the flow chart may be interchangeable.

FIG. 4 illustrates a semiconductor die structure 120 in accordance withcertain embodiments. The die structure 120 includes a plurality of vias122 extending through the semiconductor and an active region 128 on afront side. The die structure 120 also includes a backside surface 141.The region B of FIG. 4 (in dotted lines) is discussed in connection withFIGS. 5(A)-5(J), which describe processing operations in accordance withcertain embodiments.

FIG. 5(A) illustrates a blown-up view of the region B of FIG. 4, whichshows a portion of the semiconductor die structure 120 including aplurality of vias 122 and backside surface 141. If desired, the die maybe thinned from the backside surface 141. The vias 122 may be partiallyor totally filled with a conductive material such as a metal. FIG. 5(B)illustrates forming a nitride layer 150 on the backside surface 141,using a suitable deposition process. The nitride layer 150 may be formedto cover at least a portion of the vias 122. FIG. 5(C) illustratesforming a passivation layer 152 formed to cover the nitride layer, usinga suitable deposition process. An example of a passivation layer 152material is silicon oxide. FIG. 5(D) illustrates forming and patterninga first photoresist layer 154 on the passivation layer 152. Thepatterned first photoresist layer 154 acts as a mask. FIG. 5(E)illustrates removal of the unmasked portions of the passivation layer152. The removal may be carried out using a suitable process such asetching. The nitride layer 150 may act as an etch stop material. Afterthe removal operation, only a portion of the backside surface 141 iscovered with the passivation layer 152 and the first photoresist layer154.

FIG. 5(F) illustrates forming and patterning a second photoresist layer156 on portions of the remaining exposed nitride layer 150, with thesecond patterned photoresist layer 156 not being formed on nitride layerregions directly over the vias 122. FIG. 5(G) illustrates removal of thenitride layer 150 over the vias 122. The exposed nitride layer 150 overthe vias may be removed using a suitable process such as etching. FIG.5(H) illustrates removal of the second patterned photoresist layer 156and remaining first patterned photoresist layer 154, leaving a structureinclude the remaining nitride layer 150, which includes openingsextending therethrough above the vias 122, and a remaining portion ofthe passivation layer 152.

FIG. 5(I) illustrates forming an electrically conductive layer such as ametal layer 158, for example, copper, on the remaining exposed nitridelayer 150, the remaining portion of the passivation layer 152, and onthe vias 122. FIG. 5(J) illustrates removing part of the metal layer 158to expose the remaining passivation layer 152. The resultant structureincludes vias 122 electrically coupled to the metal layer 158, with theremaining passivation layer 152 acting to electrically isolate adjacentregions of the metal layer 158 from each other.

Operations such as described above and illustrated in FIGS. 5(A)-5(J)may be used for forming the backside metallization region on a die, suchas the backside metal regions 24, 34 and the backside dielectric regions26, 36 on the die structures 20, 30 in FIGS. 1 and 2.

Assemblies as described in embodiments above may find application in avariety of electronic components. In certain embodiments, a device ordevices in accordance with the present description may be embodied in acomputer system including a video controller to render information todisplay on a monitor coupled to the computer. The computer system maycomprise one or more of a desktop, workstation, server, mainframe,laptop, handheld computer, handheld gaming device, handheldentertainment device (for example, a video player), PDA (personaldigital assistant), telephony device (wireless or wired), etc.Alternatively, a device or devices in accordance with the presentdescription may be embodied in a computing device that does not includea video controller, such as a switch, router, etc.

FIGS. 6-7 illustrate certain assembly structures which may be formed inaccordance with certain embodiments. FIG. 6 illustrates a portion of anassembly, including first and second die structures 220, 230, coupled toa substrate 240. The die structures have vias 222, 232 therein. Thesedie structures may be formed to include similar electronic devices ormay be formed to include different electronic devices. Certain layers onthe die structures, including backside metal layers, dielectric layers,and active region layers, have been omitted. The die structures 220, 230include backside metallization regions that are facing each other andwhich may be coupled together using a method such as described above,for example, SAB. As seen in FIG. 6, the upper die structure 230 may bewire bonded to the substrate 240, through wire bond 251.

FIG. 7 illustrates a portion of an assembly including first, second, andthird structures 320, 330, 350, coupled to a substrate 340. Thestructures have vias 322, 332, 352 therein. These structures may besemiconductor die structures formed to include similar electronicdevices or may be formed to include different electronic devices formedtherein. Certain layers on the structures, including backside metallayers, dielectric layers, and active region layers, have been omitted.In one embodiment, the lower structure 320 and middle structure 330include backside metallization regions that are facing each other andwhich may be coupled together using a method such as described above,for example, SAB. The upper structure 350 may be coupled to the middlestructure 330 using a suitable method, for example, SAB or a solder bumpbonding process. In certain embodiments, the upper structure 350 may bewire bonded or otherwise electrically coupled to the substrate 340 or toanother device (not shown), if desired. In an alternative embodiment,the middle structure 330 and the upper structure 350 may be stacked withbackside metallization regions facing each other.

Certain embodiments as described herein may include one or moreadvantages, including, but not limited to: (i) enabling a shorter pathbetween active regions on multiple die structures, which can improvecommunication speed and efficiency; (ii) enabling the integration ofdifferent types of devices into a single assembly package; (iii)enabling efficient vertical connections between devices; (iv) providingefficient electronic connection to stacked dies; (v) minimizing thermalexpansion mismatch and stresses between stacked die structures; and (vi)forming of a compact assembly package integrating multiple diestructures. It will be appreciated that not all embodiments provide allthe advantages mentioned above, and other advantages may also beapparent to one of ordinary skill.

FIG. 8 schematically illustrates one example of an electronic systemenvironment in which aspects of described embodiments may be embodied.Other embodiments need not include all of the features specified in FIG.8, and may include alternative features not specified in FIG. 8. FIG. 8illustrates an embodiment of a device including a computer architecture400 which may utilize integrated circuit devices having a structureincluding capacitors formed in accordance with embodiments as describedabove. The architecture 400 may include a CPU 402, memory 404(including, for example, a volatile memory device), and storage 406(including, for example, a non-volatile storage device, such as magneticdisk drives, optical disk drives, etc.). The CPU 402 may be coupled to aprinted circuit board 407, which in this embodiment, may be amotherboard. The CPU 402 is an example of a package substrate assemblyformed in accordance with the embodiments described above andillustrated, for example, in FIG. 1. In one embodiment, a first CPU diemay be coupled to a second CPU die in accordance with embodimentsdescribed above, to form CPU 402. Embodiments may also include multiplesystem components formed in a single package assembly (i.e. with diestructures including different devices being coupled together). Forexample, a CPU die may be coupled to another die such as a memory chip,a chipset, or some other device, to form an assembly. A variety of othersystem components, including, but not limited to input/output devices,controllers, memory and other components, may also include structuresformed in accordance with the embodiments described above. The systemcomponents may be formed on the motherboard, or may be disposed on othercards such as daughter cards or expansion cards.

The storage 406 may comprise an internal storage device or an attachedor network accessible storage. Programs in the storage 406 may be loadedinto the memory 404 and executed by the CPU 402 in a manner known in theart. The architecture may further include a network adapter orcontroller 408 to enable communication with a network, such as anEthernet, a Fibre Channel Arbitrated Loop, etc. Further, thearchitecture may, in certain embodiments, also include a videocontroller 409, to render information on a display monitor, where thevideo controller may be embodied on a video card or integrated onintegrated circuit components mounted on the motherboard, for example.Other controllers may also be present to control other devices.

An input device 410 may be used to provide input to the CPU 402, and mayinclude, for example, a keyboard, mouse, pen-stylus, microphone, touchsensitive display screen, or any other suitable activation or inputmechanism. An output device 412 including, for example, a monitor,printer, speaker, etc., capable of rendering information transmittedfrom the CPU 402 or other component, may also be present.

While certain exemplary embodiments have been described above and shownin the accompanying drawings, it is to be understood that suchembodiments are merely illustrative and not restrictive, and thatembodiments are not restricted to the specific constructions andarrangements shown and described since modifications may occur to thosehaving ordinary skill in the art.

What is claimed:
 1. An assembly comprising: first and secondsemiconductor die structures each including a front side and a backside,the front side including an active region; a plurality of vias in eachof the first and second semiconductor die structures, the vias formingelectrical connections between the active region and the backside; andthe first and second semiconductor die structures being stacked togetherwherein the vias in the first semiconductor die structure aresubstantially aligned with the vias in the second semiconductor diestructure.
 2. The assembly of claim 1, wherein the first die structureis disposed on a substrate and wherein the second die is coupled to thesubstrate by a wire bond.
 3. The assembly of claim 1, wherein the firstdie structure is a first central processing unit and wherein the seconddie structure is a second central processing unit.
 4. The assembly ofclaim 1, wherein the first die structure is a central processing unitdie and wherein the second die structure is a memory chip.
 5. Theassembly of claim 1, further including a third die structure disposed onthe second die structure.
 6. The assembly of claim 1, wherein the firstdie structure is disposed on a substrate; wherein the first die is afirst central processing unit; and wherein the second die structure is asecond central processing unit.
 7. The assembly of claim 1, wherein thefirst die structure is disposed on a substrate; wherein the first die isa central processing unit; and wherein the second die structure is amemory chip.
 8. The assembly of claim 1, wherein the first die structureis disposed on a substrate; wherein the wherein the first die structureis a memory chip; and wherein the second die structure is a memory chip.9. An assembly comprising: first and second semiconductor die structureseach including a front side and a backside, the front side including anactive region and the backside including metal regions thereon; aplurality of vias in each of the first and second semiconductor diestructures, the vias forming electrical connections between the activeregion and the backside metal regions; and the first and secondsemiconductor die structures being stacked together wherein the vias inthe first semiconductor die structure are substantially aligned with thevias in the second semiconductor die structure.
 10. The assembly ofclaim 9, wherein the first die structure is disposed on a substrate andwherein the second die is coupled to the substrate by a wire bond. 11.The assembly of claim 9, wherein the first die structure is a firstcentral processing unit and wherein the second die structure is a secondcentral processing unit.
 12. The assembly of claim 9, wherein the firstdie structure is a central processing unit die and wherein the seconddie structure is a memory chip.
 13. The assembly of claim 9, furtherincluding a third die structure disposed on the second die structure.14. The assembly of claim 9, wherein the first die structure is disposedon a substrate; wherein the first die is a first central processingunit; and wherein the second die structure is a second centralprocessing unit.
 15. The assembly of claim 9, wherein the first diestructure is disposed on a substrate; wherein the first die is a centralprocessing unit; and wherein the second die structure is a memory chip.16. The assembly of claim 9, wherein the first die structure is disposedon a substrate; wherein the wherein the first die structure is a memorychip; and wherein the second die structure is a memory chip.
 17. Anassembly comprising: first and second semiconductor die structures eachincluding a front side and a backside, the front side including anactive region; at least one via in each of the first and secondsemiconductor die structures, the vias forming electrical connectionsbetween the active region and the backside; and the first and secondsemiconductor die structures being stacked together wherein the at leastone via in the first semiconductor die structure is electricallyconnected with the vias in the second semiconductor die structure. 18.The assembly of claim 17, wherein the first die structure is disposed ona substrate and wherein the second die is coupled to the substrate by awire bond.
 19. The assembly of claim 17, wherein the first die structureis a first central processing unit and wherein the second die structureis a second central processing unit.
 20. The assembly of claim 17,wherein the first die structure is a central processing unit die andwherein the second die structure is a memory chip.
 21. The assembly ofclaim 17, further including a third die structure disposed on the seconddie structure.
 22. The assembly of claim 17, wherein the first diestructure is disposed on a substrate; wherein the first die is a firstcentral processing unit; and wherein the second die structure is asecond central processing unit.
 23. The assembly of claim 17, whereinthe first die structure is disposed on a substrate; wherein the firstdie is a central processing unit; and wherein the second die structureis a memory chip.
 24. The assembly of claim 17, wherein the first diestructure is disposed on a substrate; wherein the wherein the first diestructure is a memory chip; and wherein the second die structure is amemory chip.